One class of nonvolatile memory devices includes phase-changeable random access memory (PRAM) devices, which offer many advantageous electrical characteristics relative to FLASH, SRAM and DRAM memory devices. PRAM devices support non-volatile data storage, random access addressing and relatively high speed read and write operations. PRAM devices may also be configured to have relatively low power consumption requirements.
The nonvolatile characteristics of the PRAM devices may be provided by configuring each memory cell with a chalcogenide alloy (e.g., GST: Ge2Sb2Te5) having programmable resistivity characteristics. For example, during a write/programming operation, the chalcogenide alloy within a memory cell may undergo resistive heating to thereby alter the resistivity of the chalcogenide alloy and cause the memory cell to be “set” into one logic state or “reset” into another logic state.
FIG. 1 illustrates a conventional diode-type PRAM cell 10, which is electrically coupled to respective bit and word lines (BL and WL). In this PRAM cell 10, the chalcogenide alloy (e.g., GST alloy) may be programmed to have a relatively high resistance state (high-R state) or a relatively low resistance state (low-R state). This state may be detected during a reading operation by biasing the bit line BL at a higher voltage relative to the word line to thereby establish a forward current path through the PRAM cell 10. The magnitude of the established current (e.g., bit line current) in the forward current path is measured to determine the state (high-R or low-R) of the cell 10.
FIG. 2 illustrates a conventional memory device 200 having a plurality of PRAM memory blocks 210a-210n therein that are electrically coupled to a column decoder/driver circuit 220. Each of these PRAM memory blocks 210a-210n is illustrated as including a plurality of memory cell blocks (CBLK), word line drivers (WD), row decoders (XDEC) and local bit line selection circuits (YD) therein. Each memory cell block (CBLK) includes a two-dimensional array of PRAM cells 10 (C) spanning multiple columns and rows. Each row within the cell block (CBLK) is associated with a corresponding local word line (WL) and each column is associated with a corresponding local bit line (BL). The word lines are driven by a word line driver (WDC), which is shown as an inverter having an output electrically coupled to one end of a local word line (WL). The local bit lines (BL) are electrically coupled to a bit line selection circuit (BDC), which is shown as an NMOS transistor having a gate terminal responsive to a column selection signal Yi and a source terminal electrically coupled to a corresponding global bit line (GBL). The global bit lines (GBL) are controlled by the column decoder/driver circuit 220, containing a column decoder (YDEC), sense amplifier (SA) and write driver (WRITED) therein. Because the size of each memory cell block (CBLK) is a function of the drive characteristics of each word line driver (WD) and bit line selection circuit (YD), the resistance of each local word line (RWL) and the resistance of each local bit line (RBL) may indirectly influence the capacity of the memory device 200 for a given layout area.
To improve PRAM device performance, some techniques have been developed to reduce local word line resistance. One such technique is disclosed in U.S. Patent Publication No. 2005/0270883 to Cho et al., entitled “Memory Device with Reduced Word Line Resistance”. As illustrated by FIG. 4 of Cho et al., a relatively long global word line may be replaced by a plurality of shorter local word lines (e.g., LWL0, LWL1 and LWL2) that are connected to respective pull-down switching devices (e.g., NMOS transistors N101, N102, N103, . . . , N106). These pull-down switching devices have gate terminals responsive to global word line signals (e.g., SWL0, SWL1 and SWL2). An additional technique is disclosed in U.S. Pat. No. 6,480,438 to Park, entitled “Providing Equal Cell Programming Conditions Across a Large and High Density Array of Phase-Change Memory Cells.” In the '438 patent, bit line and word line compensation circuits are used to minimize resistance variations across the cells of an array to thereby provide equivalent cell programming conditions. Additional PRAM devices are disclosed in an article by W. Y. Cho et al., entitled “A 0.18 um 3.0V 64 Mb Non-Volatile Phase-Transition Random-Access Memory (PRAM)”, Digest of the IEEE International Solid-State Circuits Conference, Session 2, Paper 2.1, pp. 1-2, Feb. 16, 2004. U.S. Pat. No. 6,791,867 to Tran, entitled “Selection of Memory Cells in Data Storage Devices”, discloses a non-volatile memory device having memory cells therein with programmable resistance states and shunt elements connected in series within controlled current paths. Additional PRAM devices are disclosed in: U.S. Patent Publication No. 2005/0030814 to Oh et al., entitled “Data Read Circuit for Use in a Semiconductor Memory and Method Thereof”, U.S. Patent Publication No. 2004/0246808 to Cho et al., entitled “Writing Driver Circuit of Phase-Change Memory” and U.S. Pat. No. 6,487,113 to Park et al., entitled “Programming a Phase-Change Memory with Slow Quench Time”.